1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor apparatus, in particular, a phase change random access memory apparatus and a write control method for the phase change random access memory apparatus.
2. Related Art
Phase change random access memory (PCRAM) apparatus is one of the nonvolatile memory apparatuses which is the next generation memory apparatuses that provides a high speed and enhanced number of re-writes in DRAM level performance. In particular, PCRAMs do not need to erase prior data before writing new data, and is capable of simultaneously performing a set and a reset operations.
FIG. 1 is a diagram illustrating a write operation of a typical phase change random access memory.
As a write instruction and data DQ through a data pad is inputted, an instruction control unit 10 simultaneously outputs a write command for a set operation and a write command for a reset operation.
A pulse control unit 20 generates and provides a pulse signal (IS1 or IS2 in FIG. 2) for a set operation and a pulse signal (IRS in FIG. 2) for a reset operation to a write driver 30, in response to the set write command and the reset write command.
In response to the data and input pulse signal generated by the instruction control unit 10, the write driver 30 writes set data or reset data in a corresponding memory cell in a cell array 40 in accordance with the voltage thereof.
As described above, a current PCRAM apparatus performs set/reset operations by simultaneously providing a write pulse for writing set data and a write pulse for writing reset data.
FIG. 2 is a diagram illustrating a current profile for a write operation in a typical phase change random access memory apparatus.
Writing reset data to the phase change random access memory apparatus requires a large amount of electric current to be applied for a short time which is shown as a first pulse IRS shown in FIG. 2. Meanwhile, writing set data requires a pulse having a slow quench wave such as a second pulse IS1 shown in FIG. 2, or a rectangular wave such as a third pulse IS2.
As described above, a large amount of electric current is required to program the cells of a phase change random access memory, and particularly, a large amount of programming time is required for the set data with a large amount of electric current.
Moreover, since more amount of electric current is needed to simultaneously program a plurality of cells, the electric current driving capability is limited considering the characteristics of PCRAMs that simultaneously write set/reset data. In addition, since the set/reset data is simultaneously written, the state of the cell data may be deteriorated.
Further, as the set/reset operations are simultaneously performed in a contemporary PCRAM, the write operation period is determined based on the set operation which requires relatively long programming time since more time is required for the set operation than the reset operation. This in turn results in allotting unnecessarily long time to the reset operation which ultimately adversely affects the optimization of the operation speed.
FIGS. 3A and 3B are diagrams illustrating the resistance distribution based on cell data in a cell within a phase change random access memory apparatus.
In the PCRAM, the phase change material in each cell is changed to a low resistance state to represent a set data whereas it is changed to a high resistance state to represent a reset data. Further, as shown in FIG. 3A, the resistance value of each cell has a normal distribution based on the number of cells. Here, it is ideal that there is a resistance difference RM bigger than a predetermined value between the resistance value of the phase change material representing the set data and the resistance value of the phase change material representing the reset data.
However, after a memory cell has been repeatedly written with data, and especially, set data and reset data have been simultaneously written, as shown in FIG. 3B, each of the state distributions of the cell data gradually spreads. If that happens, it is relatively hard to ensure the resistance difference between the phase change material storing the set data and the phase change material storing the reset data, such that unintended data may be stored in each memory cell.
On the other hand, the PCRAM is one of the good candidates to replace flash memories in the future as nonvolatile memories due to its high data processing speed as compared with flash memories in the related art. Here, the PCRAM does not need erasing operation which is different from the flash memories.
When a PCRAM apparatus is used in place of a flash memory apparatus, if an erasing instruction issues, the PCRAM apparatus simply stays in idle mode without performing the corresponding operation. Instead, when a programming command is generated, it simultaneously writes set data and reset data for a predetermined program period.
FIG. 4 is a diagram illustrating operational characteristics of a flash memory apparatus and a phase change random access memory apparatus, when they process a write command.
The flash memory performs erasing and programming in separate periods, in accordance with an erase command and a program command.
On the contrary, the PCRAM apparatus does not need an erase operation, and writes set data and a reset data in a single program period in response to a write instruction. Therefore, if the flash memory is replaced by the PCRAM, the PCRAM does not perform any operation during the period when the erase instruction is inputted. In contrast, it performs programming by applying a write pulse for simultaneously writing set/reset data in the period when a program instruction is inputted.
Further, it takes longer time to write set data than reset data. Accordingly, the number of programmable cells for a limited program period is necessarily limited and the erase period is inefficiently wasted.